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P R E L I M I N A R Y D A TA S H E E T
SI5319
A NY -R A TE P R E C I S I O N C L O C K MULTIPLIER/J I T T E R A T T E N U A T O R
Description
The SI5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance. The SI5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The SI5319 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The SI5319 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The SI5319 is based on Silicon Laboratories' 3rdgeneration DSPLL(R) technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the SI5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.
Features
Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (50 kHz-80 MHz) Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz) Meets OC-192 GR-253-CORE jitter specifications Clock or crystal input with manual clock selection Clock output selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236) Supports various frequency translations for Synchronous Ethernet LOL, LOS alarm outputs I2C or SPI programmable On-chip voltage regulator for 1.8 V 5%, 2.5 or 3.3 V 10% operation Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS compliant
Applications
SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 and custom FEC line cards Optical modules Wireless basestations Data converter clocking xDSL Synchronous Ethernet Test and measurement Discrete PLL replacement Broadcast video
Xtal or Refclock XO
/ NC1_LS / N32 CKIN / N31 / N2
CKOUT
DSPLL
(R)
N1_HS
Loss of Signal Loss of Lock
Signal Detect
Control
VDD (1.8, 2.5, or 3.3 V) GND
I2C/SPI Port Device Interrupt Rate Select
Xtal/Clock Select
Preliminary Rev. 0.3 1/08
Copyright (c) 2008 by Silicon Laboratories
SI5319
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SI5319
Table 1. Performance Specifications1
(VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C)
Parameter Temperature Range Supply Voltage
Symbol TA VDD
Test Condition
Supply Current
IDD
Input Clock Frequency (CKIN) Output Clock Frequency (CKOUT)
CKF CKOF
fOUT = 622.08 MHz CKOUT enabled LVPECL format output fOUT = 19.44 MHz CKOUT enabled CMOS format output Tristate/Sleep Mode Input frequency and clock multiplication ratio determined by programming device PLL dividers. Consult Silicon Laboratories configuration software DSPLLsim to determine PLL divider settings for a given input frequency/clock multiplication ratio combination. See Note 2.
Min -40 2.97 2.25 1.71 --
Typ 25 3.3 2.5 1.8 217
Max 85 3.63 2.75 1.89 243
Unit C V V V mA
--
194
220
mA
-- 0.002 0.002 970 1213
165 -- --
TBD 710 945 1134 1400
mA MHz MHz
3-Level Input Pins Input Mid Current Input Clock (CKIN) Differential Voltage Swing Common Mode Voltage
IIMM CKNDPP CKNVCM
-2 0.25
-- -- -- -- -- -- -- -- -- -- -- 230 --
2 1.9 1.4 1.7 1.95 11 60 -- VDD - 1.25 1.9 0.93 350 40
A VPP V V V ns % ns V V ps ps
Rise/Fall Time Duty Cycle (Minimum Pulse Width)
CKNTRF CKNDC
1.8 V 5% 2.5 V 10% 3.3 V 10% 20-80% Whichever is smaller
0.9 1.0 1.1 -- 40 2 VDD - 1.42 1.1 0.5 -- --
Output Clock (CKOUT) Common Mode VOCM Differential Output Swing VOD Single Ended Output VSE Swing Rise/Fall Time CKOTRF Output Duty Cycle CKODC Differential Uncertainty
LVPECL 100 load line-to-line 20-80% 100 load line-to-line measured at 50% point
Notes: 1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. 2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference Manual. In most designs an external resistor voltage divider is recommended.
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Preliminary Rev. 0.3
SI5319
Table 1. Performance Specifications1 (Continued)
(VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C)
Parameter PLL Performance Jitter Generation
Symbol JGEN
Test Condition fIN = fOUT = 622.08 MHz, LVPECL output format 50 kHz-80 MHz 12 kHz-20 MHz 800 Hz-80 MHz
Min --
Typ 0.3
Max TBD
Unit ps rms
Jitter Transfer JPK External Reference Jitter JPKEXTN Transfer Phase Noise CKOPN
-- -- -- -- -- -- -- -- -- -- --
0.3 0.4 0.05 TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD 0.1 TBD TBD TBD TBD TBD TBD TBD TBD
ps rms ps rms dB dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc
Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient
fIN = fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset SPSUBH Phase Noise @ 100 kHz Offset SPSPUR Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) Still Air
Theta JA
--
38
--
C/W
Notes: 1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. 2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference Manual. In most designs an external resistor voltage divider is recommended.
Table 2. Absolute Maximum Ratings
Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k), Except CKIN Pins ESD HBM Tolerance (100 pF, 1.5 k), CKIN Pins ESD MM Tolerance, Except CKIN Pins ESD MM Tolernace, CKIN Pins Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value -0.5 to 3.6 -0.3 to (VDD + 0.3) -55 to 150 -55 to 150 2 700 200 150 JESD78 Compliant Unit V V C C kV V V V
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.3
3
SI5319
155.52 MHz in, 622.08 MHz out
0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
Jitter Band Brick Wall, 100 Hz to 100 MHz SONET_OC48, 12 kHz to 20 MHz SONET_OC192_A, 20 kHz to 80 MHz SONET_OC192_B, 4 MHz to 80 MHz SONET_OC192_C, 50 kHz to 80 MHz Brick Wall, 800 Hz to 80 MHz Jitter, RMS 1,279 fs 315 fs 335 fs 194 fs 318 fs 343 fs
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Preliminary Rev. 0.3
SI5319
C4 1 F System Power Supply C1 0.1 F Ferrite Bead C2 0.1 F C3 0.1 F 0.1 F CKOUT+ 100 CKOUT- 0.1 F - +
VDD = 3.3 V
130 CKIN+ CKIN-
82
82
GND
VDD
130
SI5319
Option 1:
Crystal XB Crystal/RefClk Rate RATE[1:0] 0.1 F Refclk+ Refclk- Control Mode (L) Reset 0.1 F XA XB CMODE RST XA
INT_CB
Interrupt/CKIN Invalid Indicator
LOL
PLL Loss of Lock Indicator
A[2:0] SDA SCL
Serial Port Address Serial Data Serial Clock I2C Interface
Option 2:
CS
Xtal/Clock Select
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 2. SI5319 Typical Application Circuit (I2C Control Mode)
C4 1 F System Power Supply C1 0.1 F Ferrite Bead C2 0.1 F C3 0.1 F 0.1 F CKOUT+ 100 CKOUT- 0.1 F - +
VDD = 3.3 V
130 CKIN+ CKIN-
82
82
GND
VDD
130
INT_CB
Interrupt/CLKIN Invalid Indicator
SI5319
LOL PLL Loss of Lock Indicator
Option 1:
Crystal
XA
XB Crystal/RefClk Rate RATE[1:0] 0.1 F Refclk+ Refclk- Control Mode (H) Reset 0.1 F XA XB CMODE RST
SS SDO SDI SCLK
Slave Select Serial Data Out Serial Data In Serial Clock
Option 2:
SPI Interface
CS
Xtal/Clock Select
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 3. SI5319 Typical Application Circuit (SPI Control Mode)
Preliminary Rev. 0.3
5
SI5319
1. Functional Description
The SI5319 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The SI5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The SI5319 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The SI5319 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to determine the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption. This utility can be downloaded from http://www.silabs.com/timing. The SI5319 is based on Silicon Laboratories' 3rdgeneration DSPLL(R) technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The SI5319 PLL loop bandwidth is digitally programmable and supports a range from 60 Hz to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The SI5319 monitors the input clock for loss-of-signal and provides a LOS alarm when it detects missing pulses on the input clock. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The SI5319 provides a digital hold capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. During digital hold, the DSPLL freezes its VCO settings and uses its XO as its frequency reference. The SI5319 has one differential clock output. The electrical format of the clock output is programmable to support LVPECL, LVDS, CML, or CMOS loads. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply.
1.1. External Reference
A low-cost 114.285 MHz 3rd overtone crystal or an external reference oscillator is used as part of a fixedfrequency oscillator within the DSPLL. This external reference is required for the device to perform jitter attenuation. Silicon Laboratories recommends using a high quality crystal. Specific recommendations may be found in the Family Reference Manual. An external oscillator as well as other crystal frequencies can also be used as a reference for the device. In digital hold, the DSPLL remains locked to this external reference. Any changes in the frequency of this reference when the DSPLL is in digital hold will be tracked by the output of the device. Note that crystals can have temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for detailed information about the SI5319. Additional design support is available from Silicon Laboratories through your distributor. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from http://www.silabs.com/timing; click on Documentation.
6
Preliminary Rev. 0.3
SI5319
2. Pin Descriptions: SI5319
CKOUT+ 27 SDI 26 A2_SS 25 A1 24 A0 23 SDA_SDO 22 SCL 21 CS 20 GND 19 GND 10 11 12 13 14 15 16 17 18 RATE0 NC RATE1 CKIN1+ CKIN1- VDD LOL NC NC CKOUT- CMODE GND VDD NC NC NC NC
36 35 34 33 32 31 30 29 28 RST NC INT_CB NC VDD XA XB GND NC 1 2 3 4 5 6 7 8 9
GND Pad
Pin numbers are preliminary and subject to change. Pin # 1 Pin Name RST I/O I Signal Level LVCMOS Description External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are disabled during reset. The part must be programmed after a reset or power-on to get a clock output. See Family Reference Manual for details. This pin has a weak pull-up. No Connect. This pin must be left unconnected for normal operation.
2, 4, 9, 12-14, 30, 33-35 3
NC
--
--
INT_CB
O
LVCMOS
Interrupt/CKIN Invalid Indicator. This pin functions as a device interrupt output or an alarm output for CKIN. If used as an interrupt output, INT_PIN must be set to 1. The pin functions as a maskable interrupt output with active polarity controlled by the INT_POL register bit. If used as an alarm output, the pin functions as a LOS alarm indicator for CKIN. Set CK_BAD_PIN = 1 and INT_PIN = 0. 0 = CKIN present. 1 = LOS on CKIN. The active polarity is controlled by CK_BAD_POL. If no function is selected, the pin tristates.
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See SI5319 Register Map).
Preliminary Rev. 0.3
7
SI5319
Pin # 5, 10, 32 Pin Name VDD I/O VDD Signal Level Supply Description Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 F 10 0.1 F 32 0.1 F A 1.0 F should also be placed as close to the device as is practical. External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. Refer to the Family Reference Manual for interfacing to an external reference. The external reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by the RATE pins. Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. External Crystal or Reference Clock Rate. Three level inputs that select the type and rate of external crystal or reference clock to be applied to the XA/XB port. Refer to the Family Reference Manual for settings. These pins have both a weak pull-up and a weak pull-down; they default to M. The "HH" setting is not supported. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Clock Input. Differential input clock. This input can also be driven with a singleended signal. Input frequency range is 2 kHz to 710 MHz. PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator if the LOL_PIN register bit is set to 1. 0 = PLL locked. 1 = PLL unlocked. If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the LOL_POL bit. The PLL lock status will always be reflected in the LOL_INT read only register bit. Xtal/Input Clock Select. This pin selects the active DSPLL input clock, which can be a clock input or a crystal input. See the FREE_EN register for free run settings. 0 = Select clock input (CKIN). 1 = Select crystal input. This pin should not be left open. Serial Clock/Serial Clock. This pin functions as the serial clock input for both SPI and I2C modes. This pin has a weak pull-down.
7 6
XB XA
I
Analog
8, 31
GND
GND
Supply
11 15
RATE0 RATE1
I
3-Level
16 17 18
CKIN+ CKIN- LOL
I
Multi
O
LVCMOS
21
CS
I
LVCMOS
22
SCL
I
LVCMOS
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See SI5319 Register Map).
8
Preliminary Rev. 0.3
SI5319
Pin # 23 Pin Name SDA_SDO I/O I/O Signal Level LVCMOS Description Serial Data. In I2C control mode (CMODE = 0), this pin functions as the bidirectional serial data port. In SPI control mode (CMODE = 1), this pin functions as the serial data output. Serial Port Address. In I2C control mode (CMODE = 0), these pins function as hardware controlled address bits. The I2C address is 1101 [A2] [A1] [A0]. In SPI control mode (CMODE = 1), these pins are ignored. These pins have a weak pull-down. Serial Port Address/Slave Select. In I2C control mode (CMODE = 0), this pin functions as a hardware controlled address bit [A2]. In SPI control mode (CMODE = 1), this pin functions as the slave select input. This pin has a weak pull-down. Serial Data In. In I2C control mode (CMODE = 0), this pin is ignored. In SPI control mode (CMODE = 1), this pin functions as the serial data input. This pin has a weak pull-down. Output Clock. Differential output clock with a frequency range of 10 MHz to 1.4175 GHz. Output signal format is selected by SFOUT1_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical singleended clock outputs. Control Mode. Selects I2C or SPI control mode for the SI5319. 0 = I2C Control Mode 1 = SPI Control Mode Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane.
25 24
A1 A0
I
LVCMOS
26
A2_SS
I
LVCMOS
27
SDI
I
LVCMOS
29 28
CKOUT- CKOUT+
O
Multi
36
CMODE
I
LVCMOS
GND PAD
GND
GND
Supply
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See SI5319 Register Map).
Preliminary Rev. 0.3
9
SI5319
3. Ordering Guide
Ordering Part Number SI5319A-C-GM Output Clock Frequency Range 2 kHz-945 MHz 970-1134 MHz 1.213-1.417 GHz 2 kHz-808 MHz 2 kHz-346 MHz Package 36-Lead 6 x 6 mm QFN ROHS6, Pb-Free Yes Temperature Range -40 to 85 C
SI5319B-C-GM SI5319C-C-GM
36-Lead 6 x 6 mm QFN 36-Lead 6 x 6 mm QFN
Yes Yes
-40 to 85 C -40 to 85 C
10
Preliminary Rev. 0.3
SI5319
4. Package Outline: 36-Pin QFN
Figure 4 illustrates the package details for the SI5319. Table 3 lists the values for the dimensions shown in the illustration.
Figure 4. 36-Pin Quad Flat No-lead (QFN)
Table 3. Package Dimensions
Symbol Min A A1 b D D2 e E E2 3.95 3.95 0.80 0.00 0.18 Millimeters Nom 0.85 0.02 0.25 6.00 BSC 4.10 0.50 BSC 6.00 BSC 4.10 4.25 4.25 Max 0.90 0.05 0.30 L aaa bbb ccc ddd eee Symbol Min 0.50 -- -- -- -- -- -- Millimeters Nom 0.60 -- -- -- -- -- -- Max 0.70 12 0.10 0.10 0.08 0.10 0.05
Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Preliminary Rev. 0.3
11
SI5319
5. Recommended PCB Layout
Figure 5. PCB Land Pattern Diagram
12
Preliminary Rev. 0.3
SI5319
Table 4. PCB Land Pattern Dimensions
Dimension e E D E2 D2 GE GD X Y ZE ZD -- -- 4.00 4.00 4.53 4.53 -- 0.89 REF. 6.31 6.31 MIN 0.50 BSC. 5.42 REF. 5.42 REF. 4.20 4.20 -- -- 0.28 MAX
Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Preliminary Rev. 0.3
13
SI5319
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Changed 1.8 V operating range to 5%. Updated Table 1 on page 2. Updated Table 2 on page 3. Added table under Figure 1 on page 4. Updated "1. Functional Description" on page 6. Clarified "2. Pin Descriptions: SI5319" on page 7.
Revision 0.2 to Revision 0.3
Updated "2. Pin Descriptions: SI5319" on page 7.
Corrected Pins 11 and 15 description in table.
14
Preliminary Rev. 0.3
SI5319
NOTES:
Preliminary Rev. 0.3
15
SI5319
CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.3

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